1. Field of the Invention
The present invention relates to a clock generator in which a clock signal is generated by a PLL oscillation circuit.
2. Description of the Related Art
In the related art, as shown in FIG. 1, in a clock generator 100, a crystal oscillator 20 generates a reference clock signal. A programmable counter 11 performs frequency dividing on the reference clock signal. A VCO (Voltage Controlled Oscillator) 18, in which the output frequency is changeable by input voltage control, generates an output clock signal. A programmable counter 12 performs frequency dividing on the output clock signal. A phase comparator 16 compares the phases of the outputs of the programmable counters 11 and 12 with one another, and detects whether one phase advances from the other phase, whether the one phase delays from the other phase or whether the two phases are coincident with one another. Then, the phase comparator 16 outputs a phase advance signal, a phase delay signal and a phase coincident signal, appropriately. A driving circuit 17 includes a charge pump which determines the voltage to be applied to the VCO 18 based on the signal (the phase advance signal, phase delay signal or phase coincident signal) output from the phase comparator 16. The driving circuit 17 also includes a loop filter which performs filtering on the output of the charge pump.
In operation, when the phase of the output of the programmable counter 12 delays from the phase of the output of the programmable counter 11, the phase comparator 16 sends the phase delay signal to the driving circuit 17. Thereby, the driving circuit 17 raises the voltage to be applied to the VCO 18. As a result, the output frequency of the VCO 18 increases.
When the phase of the output of the programmable counter 12 advances from the phase of the output of the programmable counter 11, the phase comparator 16 sends the phase advance signal to the driving circuit 17. Thereby, the driving circuit 17 lowers the voltage to be applied to the VCO 18. As a result, the output frequency of the VCO 18 decreases.
When the phase of the output of the programmable counter 12 is coincident with the phase of the output of the programmable counter 11, the phase comparator 16 sends the phase coincident signal to the driving circuit 17. Thereby, the driving circuit 17 fixes the voltage to be applied to the VCO 18. As a result, the output frequency of the VCO 18 is fixed.
In the above-described arrangement, the frequency f.sub.1 of the clock signal output from the clock generator can be expressed as follows: EQU f.sub.1 =f.sub.0 .times.N/M
where f.sub.0 represents the frequency of the above-mentioned reference clock signal, M represents the frequency dividing ratio of the programmable counter 11 and N represents the frequency dividing ratio of the programmable counter 12.
In the clock generator 100 shown in FIG.1, data is stored in mask ROMs 103, 104, or programmable memories such as EEPROMs or RAMs. Then, the stored data is used for determining the frequency dividing ratios of the programmable counters 11 and 12. Thus, the programmable counters 11 and 12 are programmed.
It is also possible that, as in a clock generator 101, shown in FIG.2, an external microprocessor 105, or the like, programs the programmable counters 11 and 12, and thus, the frequency dividing ratios of the programmable counters 11 and 12 are determined.
In such a clock generator in the related art, which is formed in an IC (Integrated Circuit), as means for determining the frequency of the output clock signal, it is necessary to use mask ROMs, EEPROMs or RAMs, or to input control signals externally from a microprocessor or the like.
In a case of using mask ROMs, masks to be used therein are expensive. Thus, a high initial cost is required and the IC of the clock generator is expensive. Further, because a process of programming data for determining the output frequency of the clock generator is performed during a wafer process, considerable time is required for producing an IC including the clock generator which generates a clock signal of a desired frequency.
In a case of using EEPROMs or RAMs, it is necessary to input a signal externally for programming the storage device. In this case, operation is complicated and it is difficult to increase productivity. Further, it is necessary to provide extra terminals for inputting the signal on the IC. Thereby, it is not possible to miniaturize the IC chip.
In a case of inputting a control signal externally from a microprocessor or the like, it is necessary to provide extra terminals for inputting the control signal to the IC. Thereby, it is not possible to miniaturize the IC chip. Further, it is not possible that a clock signal for a microprocessor is provided by the clock generator, because the microprocessor should provide the control signal to the clock generator for causing the clock generator to generate the clock signal.